1. Field of the Invention
This invention relates to computer systems and, more particularly, to maintaining data correctness in the presence of outstanding write operations within a computer system.
2. Description of the Related Art
When transferring data between components of differing speeds, the transfer must usually take place using the slower component's transfer rate. However, write posting buffers are often used to buffer data transferred by a faster component at its maximum transfer rate until a slower component can remove that data from the write posting buffer at its transfer rate. Accordingly, write posting buffers may effectively speed-match components having different transfer rates. Write posting buffers are typically used to buffer relatively small data transfers (e.g., several bytes) to system memory.
Using a write-posting buffer may introduce additional latency or complication for read operations in order to maintain data correctness. Some write-posting buffers block all outstanding reads until any outstanding writes have completed to memory in order to avoid providing stale data in response to a read. Other write posting buffers employ read ahead mechanisms, which allow reads to addresses that are not targeted by any of the posted writes to progress before the outstanding posted writes have completed. Still other write posting buffers include read forwarding mechanisms, which allow a read to complete by forwarding data from the posted write buffer if the read targets an address targeted by an outstanding write.